Table of Contents

• A low power fast wakeup flash memory system for embedded SOCsKarthik Ramanan, Jacob Williams. 1-4 [doi]
• Low power Adiabatic Logic based on 2PC2ALMei Han, Yasuhiro Takahashi, Toshikazu Sekine. 1-4 [doi]
• Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologiesLouise De Conti, Thomas Bedecarrats, Maud Vinet, Sorin Cristoloveanu, Philippe Galy. 1-4 [doi]
• Layout engineering to suppress hysteresis of negative capacitance FinFETEunah Ko, Jaesung Jo, Changhwan Shin, Bich-Yen Nguyen. 1-3 [doi]
• SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and AutomotiveTakumi Hasegawa, Yoshiki Yamamoto, Hideki Makiyama, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi. 1-4 [doi]
• Statistical circuit performance dependency analysis via sparse relevance kernel machineHonghuang Lin, Asad M. Khan, Peng Li. 1-4 [doi]
• NRAM status and prospectsD. C. Gilmer, Thomas Rueckes, L. Cleveland, Darlene Viviani. 1-4 [doi]
• Interfacial transition layer in thermally grown SiO2 film on 4H-SiCRyu Hasunuma. 1-4 [doi]
• A resistance model of integrated octagonal-shaped Hall sensor using JFET compact modelMilos Skalsky, Stanislav Banas, Vaclav Panko. 1-4 [doi]
• Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-ChipHai-Phong Phan, Xuan-Tu Tran, Tomohiro Yoneda. 1-4 [doi]
• Dedicated technology threshold voltage tuning for 6T SRAM beyond N7Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene. 1-4 [doi]
• Yield and energy tradeoffs of an NVLatch design using radial samplingAdam Issa, Rouwaida Kanj, Ali Chehab, Rajiv V. Joshi. 1-4 [doi]
• Wideband inductorless CMOS RF front-end for LTE receiversEman Badr, Heba A. Shawkey, Yehea Ismail, Abdelhalim Zekry. 1-4 [doi]
• SOI CMOS technology for quantum information processingL. Hutin, B. Bertrand, R. Maurand, M. Urdampilleta, B. Jadot, H. Bohuslavskyi, L. Bourdet, Yann-Michel Niquet, Xavier Jehl, Sylvain Barraud, C. Bauerle, T. Meunier, Marc Sanquer, S. De Franceschi, Maud Vinet. 1-4 [doi]
• Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMSTakuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi. 1-4 [doi]
• Integrated electrical sensing for high-throughput bioanalyticsCarlotta Guiducci. 1-3 [doi]
• FD-SOI material enabling CMOS technology disruption from 65nm to 12nm and beyondW. Schwarzenbach, M. Sellier, B.-Y. Nguyen, C. Girard, C. Maleville. 1-2 [doi]
• Advances of the development of a ferroelectric field-effect transistor on Ge(001)Patrick Ponath, Agham B. Posadas, Yuan Ren, Xiaoyu Wu, Keji Lai, Alex Demkov, Michael Schmidt, Ray Duffy, Paul K. Hurley, Jian Wang, Chadwin Young, Rama K. Vasudevan, M. Baris Okatan, S. Jesse, Sergei V. Kalinin. 1-3 [doi]
• A 910nW delta sigma modulator using 65nm SOTB technology for mixed signal IC of IoT applicationsKoichiro Ishibashi, Junya Kikuchi, Nobuyuki Sugii. 1-3 [doi]
• III-V-based low power CMOS devices on Si platformS. Takagi, D. H. Ahn, T. Gotow, M. Noguchi, K. Nishi, S. H. Kim, M. Yokoyama, C. Y. Chang, S.-H. Yoon, C. Yokoyama, M. Takenaka. 1-4 [doi]
• Dadda Multiplier designs using memristorsLauren Guckert, Earl E. Swartzlander Jr.. 1-4 [doi]
• Microstructure and ferroelectricity of barium titanate thin films on Si for integrated photonicsKristy J. Kormondy, Alexander A. Demkov, Youri Popoff, Marilyne Sousa, Felix Eltes, Daniele Caimi, Chiara Marchiori, Jean Fompeyrine, Stefan Abel. 1-2 [doi]
• Fluids energy harvesting system with low cut-in velocity piezoelectric MEMSG. E. Biccario, M. De Vittorio, S. D'Amico. 1-4 [doi]
• SRAM designs for 5nm node and beyond: Opportunities and challengesTrong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Alessio Spessot, Diederik Verkest, Anda Mocuta. 1-4 [doi]
• Innovative and 3D stacking Micro Electro Mechanical Systems (I-MEMS) for power savingKiyoshi Mori, Giang Dao, Ziep Tran, Michael Ramon, Jason Woo, Peng Lu. 1-3 [doi]
• Design considerations for optimization of pull-in stability margin in electrostatic N/MEM relaysGiulia Usai, Louis Hutin, Jose Luis Munoz-Gamarra, Thomas Ernst, Maud Vinet, Philip X.-L. Feng. 1-4 [doi]
• Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistorD. H. Triyoso, G. R. Mulfinger, K. Hempel, H. Tao, F. Koehler, L. Kang, A. Kumar, T. McArdle, J. Holt, A. L. Child, S. Straub, F. Ludwig, Z. Chen, J. Kluth, R. Carter. 1-4 [doi]
• Electrons, phonons, and unconventional applications of 2D materialsEric Pop, Eilam Yalon, Miguel Munoz-Rojo, Michal Mleczko, Chris English, Ning Wang, Kirby Smithe, Saurabh Suryavanshi, Isha Datye, Connor McClellan, Alex Gabourie. 1-2 [doi]
• FDSOI vs FinFET: differentiating device features for ultra low power & IoT applicationsO. Weber. 1-3 [doi]