Atsuki Kobayashi, Yuya Nishio, Kenya Hayashi, Kazuo Nakazato, Kiichi Niitsu. A 350-mV, under-200-ppm allan deviation floor gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS. In 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, CA, USA, April 8-11, 2018. pages 1-4, IEEE, 2018. [doi]
Abstract is missing.