Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance

M. Kobrinsky, J. D. Silva, E. Mannebach, S. Mills, M. Abd El Qader, O. Adebayo, N. Arkali Radhakrishna, M. Beasley, J. Chawla, S. Chugh, A. Dasgupta, U. Desai, E. De Re, G. Dewey, T. Edwards, C. Engel, V. Gudmundsson, J. Hicks, B. Krist, R. Mehandru, Inanc Meric, P. Morrow, D. Nandi, P. Patel, R. Ramamurthy, D. Samanta, L. Shoer, A. St Amour, L. H. Tan, Sukru Yemenicioglu, X. Wang, T. Ghani. Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]

Authors

M. Kobrinsky

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J. D. Silva

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E. Mannebach

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S. Mills

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M. Abd El Qader

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O. Adebayo

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N. Arkali Radhakrishna

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M. Beasley

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J. Chawla

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S. Chugh

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A. Dasgupta

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U. Desai

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E. De Re

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G. Dewey

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T. Edwards

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C. Engel

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V. Gudmundsson

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J. Hicks

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B. Krist

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R. Mehandru

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Inanc Meric

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P. Morrow

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D. Nandi

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P. Patel

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R. Ramamurthy

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D. Samanta

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L. Shoer

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A. St Amour

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L. H. Tan

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Sukru Yemenicioglu

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X. Wang

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T. Ghani

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