Design Validation: Formal Verification vs. Simulation vs. Functional Testing

Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner. Design Validation: Formal Verification vs. Simulation vs. Functional Testing. In 14th IEEE VLSI Test Symposium (VTS 96), April 28 - May 1, 1996, Princeton, NJ, USA. pages 364-365, IEEE Computer Society, 1996. [doi]

Authors

Bernd Koenemann

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J. Monzel

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T. Powell

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N. Saxena

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K. Wagner

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