Design Validation: Formal Verification vs. Simulation vs. Functional Testing

Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner. Design Validation: Formal Verification vs. Simulation vs. Functional Testing. In 14th IEEE VLSI Test Symposium (VTS 96), April 28 - May 1, 1996, Princeton, NJ, USA. pages 364-365, IEEE Computer Society, 1996. [doi]

@inproceedings{KoenemannMPSW96,
  title = {Design Validation: Formal Verification vs. Simulation vs. Functional Testing},
  author = {Bernd Koenemann and J. Monzel and T. Powell and N. Saxena and K. Wagner},
  year = {1996},
  url = {http://csdl.computer.org/comp/proceedings/vts/1996/7304/00/73040364.pdf},
  tags = {testing, design},
  researchr = {https://researchr.org/publication/KoenemannMPSW96},
  cites = {0},
  citedby = {0},
  pages = {364-365},
  booktitle = {14th IEEE VLSI Test Symposium (VTS 96),  April 28 - May 1, 1996, Princeton, NJ, USA},
  publisher = {IEEE Computer Society},
}