Naoaki Kokubun, Akira Yamaga, Hironori Uchikawa, Daiki Watanabe. Circuit-Size Reduction for Parallel Chien Search using Minimal Polynomial Degree Reduction. In IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019. pages 1-5, IEEE, 2019. [doi]
@inproceedings{KokubunYUW19, title = {Circuit-Size Reduction for Parallel Chien Search using Minimal Polynomial Degree Reduction}, author = {Naoaki Kokubun and Akira Yamaga and Hironori Uchikawa and Daiki Watanabe}, year = {2019}, doi = {10.1109/ISCAS.2019.8702075}, url = {https://doi.org/10.1109/ISCAS.2019.8702075}, researchr = {https://researchr.org/publication/KokubunYUW19}, cites = {0}, citedby = {0}, pages = {1-5}, booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019}, publisher = {IEEE}, isbn = {978-1-7281-0397-6}, }