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Logic Locking Designs at Transistor Level for Full Adders

Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad. Logic Locking Designs at Transistor Level for Full Adders. In IEEE International Symposium on Smart Electronic Systems, iSES 2022, Warangal, India, December 18-22, 2022. pages 289-292, IEEE, 2022. [doi]

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Sandeep Kolla

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Ayesha Sk

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Sreehari Veeramachaneni

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Sk. Noor Mahammad

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