The following publications are possibly variants of this publication:
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- Hardware Reduction for Lut-Based Mealy FSMsAlexander Barkalov, Larysa Titarenko, Kamil Mielcarek. amcs, 28(3):595-607, 2018. [doi]
- Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSMAlexander Barkalov, Larysa Titarenko, Slawomir Chmielewski. amcs, 17(4):565-575, 2007. [doi]
- Design of EMB-Based Moore FSMsMalgorzata Kolopienczyk, Larysa Titarenko, Alexander Barkalov. jcsc, 26(7):1-23, 2017. [doi]
- Hardware reduction for FSM - Based control units using PAL technologyAlexander Barkalov, Larysa Titarenko, Slawomir Chmielewski. ewdts 2010: 21-24 [doi]
- Improving Characteristics of LUT-Based Moore FSMsAlexander Barkalov, Larysa Titarenko, Slawomir Chmielewski. access, 8:155306-155318, 2020. [doi]
- Code sharing in CPLD-based Moore FSMsAlexander Barkalov, Larysa Titarenko, Jacek Bieganowski. mocast 2017: 1-4 [doi]
- Encoding of Microoperations in FPGA-Based Moore FSMsAlexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek. mocast 2019: 1-4 [doi]
- Reduction in the number of PAL macrocells for Moore FSM implemented with CPLDAlexander Barkalov, Larysa Titarenko, Slawomir Chmielewski. ewdts 2010: 390-394 [doi]
- Hardware Reduction for FSMs With Extended State CodesAlexander Barkalov 0001, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz. access, 12:42369-42384, 2024. [doi]