Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM

Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki. Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM. IEICE Trans. Commun., 104-B(2):149-157, 2021. [doi]

Abstract

Abstract is missing.