A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier

Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka. A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012. pages 84-86, IEEE, 2012. [doi]

@inproceedings{KousaiOYKN12-0,
  title = {A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier},
  author = {Shouhei Kousai and Kohei Onizuka and Takashi Yamaguchi and Yasuhiko Kuriyama and Masami Nagaoka},
  year = {2012},
  doi = {10.1109/ISSCC.2012.6176880},
  url = {http://dx.doi.org/10.1109/ISSCC.2012.6176880},
  researchr = {https://researchr.org/publication/KousaiOYKN12-0},
  cites = {0},
  citedby = {0},
  pages = {84-86},
  booktitle = {2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012},
  publisher = {IEEE},
  isbn = {978-1-4673-0376-7},
}