Andrzej Krasniewski. Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs. In Bernd Straube, Milos Drutarovský, Michel Renovell, Peter Gramata, Mária Fischerová, editors, Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008. pages 74-79, IEEE Computer Society, 2008. [doi]
Abstract is missing.