2Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores

Florian Kriebel, Arun Subramaniyan, Semeen Rehman, Segnon Jean Bruno Ahandagbe, Muhammad Shafique, Jörg Henkel. 2Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores. In Gabriela Nicolescu, Andreas Gerstlauer, editors, 2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015, Amsterdam, Netherlands, October 4-9, 2015. pages 1-10, IEEE, 2015. [doi]

@inproceedings{KriebelSRASH15,
  title = {2Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores},
  author = {Florian Kriebel and Arun Subramaniyan and Semeen Rehman and Segnon Jean Bruno Ahandagbe and Muhammad Shafique and Jörg Henkel},
  year = {2015},
  url = {http://dl.acm.org/citation.cfm?id=2830841},
  researchr = {https://researchr.org/publication/KriebelSRASH15},
  cites = {0},
  citedby = {0},
  pages = {1-10},
  booktitle = {2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015, Amsterdam, Netherlands, October 4-9, 2015},
  editor = {Gabriela Nicolescu and Andreas Gerstlauer},
  publisher = {IEEE},
  isbn = {978-1-4673-8321-9},
}