Florian Kriebel, Arun Subramaniyan, Semeen Rehman, Segnon Jean Bruno Ahandagbe, Muhammad Shafique, Jörg Henkel. 2Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores. In Gabriela Nicolescu, Andreas Gerstlauer, editors, 2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015, Amsterdam, Netherlands, October 4-9, 2015. pages 1-10, IEEE, 2015. [doi]
Abstract is missing.