A procedure for software synthesis from VHDL models

Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee. A procedure for software synthesis from VHDL models. In Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997. pages 593-598, IEEE, 1997. [doi]

@inproceedings{KrishnaswamyGB97-0,
  title = {A procedure for software synthesis from VHDL models},
  author = {Venkatram Krishnaswamy and Rajesh Gupta and Prithviraj Banerjee},
  year = {1997},
  doi = {10.1109/ASPDAC.1997.600341},
  url = {http://dx.doi.org/10.1109/ASPDAC.1997.600341},
  researchr = {https://researchr.org/publication/KrishnaswamyGB97-0},
  cites = {0},
  citedby = {0},
  pages = {593-598},
  booktitle = {Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997},
  publisher = {IEEE},
  isbn = {0-7803-3663-1},
}