Chien-Wei Kuan, Hung-Chih Lin. 2 in 65nm CMOS. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012. pages 274-276, IEEE, 2012. [doi]
@inproceedings{KuanL12-0,
title = {2 in 65nm CMOS},
author = {Chien-Wei Kuan and Hung-Chih Lin},
year = {2012},
doi = {10.1109/ISSCC.2012.6177013},
url = {http://dx.doi.org/10.1109/ISSCC.2012.6177013},
researchr = {https://researchr.org/publication/KuanL12-0},
cites = {0},
citedby = {0},
pages = {274-276},
booktitle = {2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012},
publisher = {IEEE},
isbn = {978-1-4673-0376-7},
}