A CMOS gate array with dynamic-termination GTL I/O circuits

Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito. A CMOS gate array with dynamic-termination GTL I/O circuits. In 1995 International Conference on Computer Design (ICCD 95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings. pages 25, IEEE Computer Society, 1995. [doi]

Abstract

Abstract is missing.