Low Power Optimization of Hybrid Logic Full Adder Design using FinFET 32nm Technology - researchr publication authors

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Sanjeev Kumar, Kanika Jindal, Pavan Kumar Shukla. Low Power Optimization of Hybrid Logic Full Adder Design using FinFET 32nm Technology. In 7th International Conference on Contemporary Computing and Informatics, IC3I 2024, Greater Noida, India, September 18-20, 2024. pages 345-349, IEEE, 2024. [doi]

This author has not been identified. Look up 'Sanjeev Kumar' in GoogleThis author has not been identified. Look up 'Kanika Jindal' in GoogleThis author has not been identified. Look up 'Pavan Kumar Shukla' in Google

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