Sanjeev Kumar, Kanika Jindal, Pavan Kumar Shukla. Low Power Optimization of Hybrid Logic Full Adder Design using FinFET 32nm Technology. In 7th International Conference on Contemporary Computing and Informatics, IC3I 2024, Greater Noida, India, September 18-20, 2024. pages 345-349, IEEE, 2024. [doi]
Abstract is missing.