Rakesh Kumar, Dean M. Tullsen. Compiling for instruction cache performance on a multithreaded architecture. In Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002. pages 419-429, ACM/IEEE, 2002. [doi]
@inproceedings{KumarT02,
title = {Compiling for instruction cache performance on a multithreaded architecture},
author = {Rakesh Kumar and Dean M. Tullsen},
year = {2002},
doi = {10.1145/774861.774906},
url = {http://doi.acm.org/10.1145/774861.774906},
tags = {caching, architecture, compiler},
researchr = {https://researchr.org/publication/KumarT02},
cites = {0},
citedby = {0},
pages = {419-429},
booktitle = {Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002},
publisher = {ACM/IEEE},
isbn = {0-7695-1859-1},
}