Balakrishna Kumthekar, Fabio Somenzi. Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs. In 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France. pages 202-207, IEEE Computer Society, 2000. [doi]
@inproceedings{KumthekarS00,
title = {Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs},
author = {Balakrishna Kumthekar and Fabio Somenzi},
year = {2000},
url = {http://csdl.computer.org/comp/proceedings/date/2000/0537/00/05370202abs.htm},
tags = {optimization, logic},
researchr = {https://researchr.org/publication/KumthekarS00},
cites = {0},
citedby = {0},
pages = {202-207},
booktitle = {2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France},
publisher = {IEEE Computer Society},
isbn = {0-7695-0537-6},
}