Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs

Balakrishna Kumthekar, Fabio Somenzi. Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs. In 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France. pages 202-207, IEEE Computer Society, 2000. [doi]

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