Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays - researchr publication authors

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H. T. Kung, Bradley McDanel, Sai Qian Zhang, Xin Dong, Chih-Chiang Chen. Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays. In 30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019. pages 42-50, IEEE, 2019. [doi]

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