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Ko-Chi Kuo, Chi-Wen Chou. Low Power Multiplier with Bypassing and Tree Strucuture. In IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006. pages 602-605, IEEE, 2006. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A Low-Power Multiplier with Bypassing Logic and Operand DecompositionKo-Chi Kuo, Chi-Wen Chou. imecs 2006: 217-220 Low power and high speed multiplier design with row bypassing and parallel architectureKo-Chi Kuo, Chi-Wen Chou. mj, 41(10):639-650, 2010. [doi]
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