Chia-Yu Kuo, Wei-Chien Cheng, Yi-Chung Wu. A 16-nm 24.8 Mbps/mJ Utilization-Aware Dynamic Allocation Read Mapping Accelerator for Next-Generation Sequencing. In IEEE International Symposium on Circuits and Systems, ISCAS 2026, Shanghai, China, May 24-28, 2026. pages 1649-1653, IEEE, 2026. [doi]
Abstract is missing.