A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit - researchr publication bibtex

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James B. Kuo, K. W. Su, J. H. Lou. A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit. In ISCAS. pages 323-326, 1994.

@inproceedings{KuoSL94,
  title = {A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit},
  author = {James B. Kuo and K. W. Su and J. H. Lou},
  year = {1994},
  tags = {architecture, logic},
  researchr = {https://researchr.org/publication/KuoSL94},
  cites = {0},
  citedby = {0},
  pages = {323-326},
  booktitle = {ISCAS},
}

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