The following publications are possibly variants of this publication:
- A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuitJames B. Kuo, K. W. Su, J. H. Lou. jssc, 30(8):950-954, August 1995. [doi]
- A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable for VLSI using low-voltage BiCMOS technologyJames B. Kuo, K. W. Su, J. H. Lou, S. S. Chen, C. S. Chiang. jssc, 30(1):73-75, January 1995. [doi]
- A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSIJames B. Kuo, H. P. Chen, H.-J. Huang. iscas 1993: 2027-2030