A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit

James B. Kuo, K. W. Su, J. H. Lou. A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. J. Solid-State Circuits, 30(8):950-954, August 1995. [doi]

Abstract

Abstract is missing.