James B. Kuo, K. W. Su, J. H. Lou. A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. J. Solid-State Circuits, 30(8):950-954, August 1995. [doi]
@article{KuoSL95,
title = {A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit},
author = {James B. Kuo and K. W. Su and J. H. Lou},
year = {1995},
month = {August},
doi = {10.1109/4.400440},
url = {https://doi.org/10.1109/4.400440},
researchr = {https://researchr.org/publication/KuoSL95},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {30},
number = {8},
pages = {950-954},
}