Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures - researchr publication

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George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi. Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. J. Low Power Electronics, 5(1):58-68, 2009. [doi]

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