Jacqueline Lagasse, Christopher Bartoli, Wayne Burleson. Combining Clock and Voltage Noise Countermeasures Against Power Side-Channel Analysis. In 30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019. pages 214-217, IEEE, 2019. [doi]
@inproceedings{LagasseBB19,
title = {Combining Clock and Voltage Noise Countermeasures Against Power Side-Channel Analysis},
author = {Jacqueline Lagasse and Christopher Bartoli and Wayne Burleson},
year = {2019},
doi = {10.1109/ASAP.2019.00009},
url = {https://doi.org/10.1109/ASAP.2019.00009},
researchr = {https://researchr.org/publication/LagasseBB19},
cites = {0},
citedby = {0},
pages = {214-217},
booktitle = {30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019},
publisher = {IEEE},
isbn = {978-1-7281-1601-3},
}