Implement 32-bit RISC-V Architecture Processor using Verilog HDL - researchr publication

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Jin-Yang Lai, Chiung-An Chen, Shih-Lun Chen, Chun-Yu Su. Implement 32-bit RISC-V Architecture Processor using Verilog HDL. In International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2021, Hualien City, Taiwan, November 16-19, 2021. pages 1-2, IEEE, 2021. [doi]

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