Low Latency VLSI Architecture for the Radix-4 CORDIC Algorithm - researchr publication authors

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Boppana Lakshmi, A. S. Dhar. Low Latency VLSI Architecture for the Radix-4 CORDIC Algorithm. In IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, ICIIS 2008, Kharagpur, India, December 8-10, 2008. pages 1-5, IEEE, 2008. [doi]

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