Boppana Lakshmi, A. S. Dhar. Low Latency VLSI Architecture for the Radix-4 CORDIC Algorithm. In IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, ICIIS 2008, Kharagpur, India, December 8-10, 2008. pages 1-5, IEEE, 2008. [doi]
@inproceedings{LakshmiD08,
title = {Low Latency VLSI Architecture for the Radix-4 CORDIC Algorithm},
author = {Boppana Lakshmi and A. S. Dhar},
year = {2008},
doi = {10.1109/ICIINFS.2008.4798377},
url = {https://doi.org/10.1109/ICIINFS.2008.4798377},
researchr = {https://researchr.org/publication/LakshmiD08},
cites = {0},
citedby = {0},
pages = {1-5},
booktitle = {IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, ICIIS 2008, Kharagpur, India, December 8-10, 2008},
publisher = {IEEE},
}