A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40% - researchr publication

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Nivedita Laskar, Suman Debnath, Alak Majumder, Bidyut K. Bhattacharyya. A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%. Journal of Circuits, Systems, and Computers, 27(3):1-20, 2018. [doi]

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