A 15-MHz Bandwidth 1-0 MASH $\Sigma \Delta $ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR

Seung-Chul Lee, Yun Chiu. A 15-MHz Bandwidth 1-0 MASH $\Sigma \Delta $ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR. J. Solid-State Circuits, 49(3):695-707, 2014. [doi]

@article{LeeC14-6,
  title = {A 15-MHz Bandwidth 1-0 MASH $\Sigma \Delta $ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR},
  author = {Seung-Chul Lee and Yun Chiu},
  year = {2014},
  doi = {10.1109/JSSC.2014.2304364},
  url = {http://dx.doi.org/10.1109/JSSC.2014.2304364},
  researchr = {https://researchr.org/publication/LeeC14-6},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {49},
  number = {3},
  pages = {695-707},
}