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Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture

Cheng-Yu Lee, Min-Chin Hung, Rong-Guey Chang. Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture. Concurrency - Practice and Experience, 26(1):134-151, 2014. [doi]

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Cheng-Yu Lee

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Min-Chin Hung

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Rong-Guey Chang

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