Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim. An on-chip cache compression technique to reduce decompression overhead and design complexity. Journal of Systems Architecture, 46(15):1365-1382, 2000. [doi]
@article{LeeHK00-0,
title = {An on-chip cache compression technique to reduce decompression overhead and design complexity},
author = {Jang-Soo Lee and Won-Kee Hong and Shin-Dug Kim},
year = {2000},
doi = {10.1016/S1383-7621(00)00030-8},
url = {http://dx.doi.org/10.1016/S1383-7621(00)00030-8},
tags = {caching, design complexity, design},
researchr = {https://researchr.org/publication/LeeHK00-0},
cites = {0},
citedby = {0},
journal = {Journal of Systems Architecture},
volume = {46},
number = {15},
pages = {1365-1382},
}