Chun C. Lee, Cho-Ying Lu, Ramya Narayanaswamy, Jad B. Rizk. A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS. In Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015. pages 62, IEEE, 2015. [doi]
@inproceedings{LeeLNR15,
title = {A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS},
author = {Chun C. Lee and Cho-Ying Lu and Ramya Narayanaswamy and Jad B. Rizk},
year = {2015},
doi = {10.1109/VLSIC.2015.7231328},
url = {http://dx.doi.org/10.1109/VLSIC.2015.7231328},
researchr = {https://researchr.org/publication/LeeLNR15},
cites = {0},
citedby = {0},
pages = {62},
booktitle = {Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015},
publisher = {IEEE},
isbn = {978-4-86348-502-0},
}