Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition

Chiou-Yng Lee, Pramod Kumar Meher, Chia-Chen Fan, Shyan-Ming Yuan. Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition. IEEE Trans. VLSI Syst., 25(2):735-746, 2017. [doi]

@article{LeeMFY17,
  title = {Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition},
  author = {Chiou-Yng Lee and Pramod Kumar Meher and Chia-Chen Fan and Shyan-Ming Yuan},
  year = {2017},
  doi = {10.1109/TVLSI.2016.2605183},
  url = {http://dx.doi.org/10.1109/TVLSI.2016.2605183},
  researchr = {https://researchr.org/publication/LeeMFY17},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {25},
  number = {2},
  pages = {735-746},
}