Yu-Huei Lee, Shen-Yu Peng, Alex Chun-Hsien Wu, Chao-Chang Chiu, Yao-Yi Yang, Ming-Hsin Huang, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Ching-Yuan Yeh, Chen-Chih Huang, Chao-Cheng Lee. A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance. In Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012. pages 178-179, IEEE, 2012. [doi]
@inproceedings{LeePWCYHCLWYHL12,
title = {A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance},
author = {Yu-Huei Lee and Shen-Yu Peng and Alex Chun-Hsien Wu and Chao-Chang Chiu and Yao-Yi Yang and Ming-Hsin Huang and Ke-Horng Chen and Ying-Hsi Lin and Shih-Wei Wang and Ching-Yuan Yeh and Chen-Chih Huang and Chao-Cheng Lee},
year = {2012},
doi = {10.1109/VLSIC.2012.6243848},
url = {http://dx.doi.org/10.1109/VLSIC.2012.6243848},
researchr = {https://researchr.org/publication/LeePWCYHCLWYHL12},
cites = {0},
citedby = {0},
pages = {178-179},
booktitle = {Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012},
publisher = {IEEE},
isbn = {978-1-4673-0848-9},
}