Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18/spl mu/m CMOS Technology"

Jri Lee, Behzad Razavi. Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18/spl mu/m CMOS Technology". J. Solid-State Circuits, 40(2):559, 2005. [doi]

@article{LeeR05-4,
  title = {Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18/spl mu/m CMOS Technology"},
  author = {Jri Lee and Behzad Razavi},
  year = {2005},
  doi = {10.1109/JSSC.2004.842373},
  url = {https://doi.org/10.1109/JSSC.2004.842373},
  researchr = {https://researchr.org/publication/LeeR05-4},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {40},
  number = {2},
  pages = {559},
}