32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation - researchr publication authors

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Tzung-Je Lee, Kai-Wei Ruan, Chua-Chin Wang. 32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation. In 2014 IEEE International Conference on IC Design & Technology, ICICDT 2014, Austin, TX, USA, May 28-30, 2014. pages 1-4, IEEE, 2014. [doi]

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