A shift register architecture for high-speed data sorting

Chen-Yi Lee, Jer-Min Tsai. A shift register architecture for high-speed data sorting. VLSI Signal Processing, 11(3):273-280, 1995. [doi]

Authors

Chen-Yi Lee

This author has not been identified. Look up 'Chen-Yi Lee' in Google

Jer-Min Tsai

This author has not been identified. Look up 'Jer-Min Tsai' in Google