An on-chip self-test architecture with test patterns recorded in scan chains

Kuen-Jong Lee, Pin-Hao Tang, Michael A. Kochte. An on-chip self-test architecture with test patterns recorded in scan chains. In 2016 IEEE International Test Conference, ITC 2016, Fort Worth, TX, USA, November 15-17, 2016. pages 1-10, IEEE, 2016. [doi]

@inproceedings{LeeTK16-2,
  title = {An on-chip self-test architecture with test patterns recorded in scan chains},
  author = {Kuen-Jong Lee and Pin-Hao Tang and Michael A. Kochte},
  year = {2016},
  doi = {10.1109/TEST.2016.7805865},
  url = {http://dx.doi.org/10.1109/TEST.2016.7805865},
  researchr = {https://researchr.org/publication/LeeTK16-2},
  cites = {0},
  citedby = {0},
  pages = {1-10},
  booktitle = {2016 IEEE International Test Conference, ITC 2016, Fort Worth, TX, USA, November 15-17, 2016},
  publisher = {IEEE},
  isbn = {978-1-4673-8773-6},
}