Chih-Wei Lee, Hwa-Yi Tseng, Chi-Lien Kuo, Chien-Nan Jimmy Liu, Chin Hsia. Layout placement optimization with isolation rings for high-voltage VLSI circuits. In 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, April 24-27, 2017. pages 1-4, IEEE, 2017. [doi]
Abstract is missing.