Jui-Sheng Lee, Sheng-Han Wang, Chih-Tai Chou, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo. An inter-frame/inter-view cache architecture design for multi-view video decoders. In Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2012, Hollywood, CA, USA, December 3-6, 2012. pages 1-4, IEEE, 2012. [doi]
@inproceedings{LeeWCCCG12,
title = {An inter-frame/inter-view cache architecture design for multi-view video decoders},
author = {Jui-Sheng Lee and Sheng-Han Wang and Chih-Tai Chou and Cheng-An Chien and Hsiu-Cheng Chang and Jiun-In Guo},
year = {2012},
url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6411972},
researchr = {https://researchr.org/publication/LeeWCCCG12},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2012, Hollywood, CA, USA, December 3-6, 2012},
publisher = {IEEE},
isbn = {978-1-4673-4863-8},
}