An O(n) Parallel Shortest Path Algorithm and Its Hardware Implementation

Jaehwan John Lee, Xiang Xiao. An O(n) Parallel Shortest Path Algorithm and Its Hardware Implementation. In Hamid R. Arabnia, Ashu M. G. Solo, editors, Proceedings of the 2010 International Conference on Computer Design, CDES 2010, July 12-15, 2010, Las Vegas Nevada, USA. pages 117-123, CSREA Press, 2010.

@inproceedings{LeeX10,
  title = {An O(n) Parallel Shortest Path Algorithm and Its Hardware Implementation},
  author = {Jaehwan John Lee and Xiang Xiao},
  year = {2010},
  researchr = {https://researchr.org/publication/LeeX10},
  cites = {0},
  citedby = {0},
  pages = {117-123},
  booktitle = {Proceedings of the 2010 International Conference on Computer Design, CDES 2010, July 12-15, 2010, Las Vegas Nevada, USA},
  editor = {Hamid R. Arabnia and Ashu M. G. Solo},
  publisher = {CSREA Press},
  isbn = {1-60132-135-X},
}