A dual-retention time architecture towards secure and high performance STT-RAM main memory subsystem

Taemin Lee, Sungjoo Yoo. A dual-retention time architecture towards secure and high performance STT-RAM main memory subsystem. In International SoC Design Conference, ISOCC 2016, Jeju, South Korea, October 23-26, 2016. pages 313-314, IEEE, 2016. [doi]

@inproceedings{LeeY16a,
  title = {A dual-retention time architecture towards secure and high performance STT-RAM main memory subsystem},
  author = {Taemin Lee and Sungjoo Yoo},
  year = {2016},
  doi = {10.1109/ISOCC.2016.7799803},
  url = {http://dx.doi.org/10.1109/ISOCC.2016.7799803},
  researchr = {https://researchr.org/publication/LeeY16a},
  cites = {0},
  citedby = {0},
  pages = {313-314},
  booktitle = {International SoC Design Conference, ISOCC 2016, Jeju, South Korea, October 23-26, 2016},
  publisher = {IEEE},
  isbn = {978-1-5090-3219-8},
}