FPGA timing, power, signal integrity and other challenges at 65 and 45 nm

Paul Leventis. FPGA timing, power, signal integrity and other challenges at 65 and 45 nm. In Tarek A. El-Ghazawi, Yao-Wen Chang, Juinn-Dar Huang, Proshanta Saha, editors, 2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008. IEEE, 2008. [doi]

@inproceedings{Leventis08,
  title = {FPGA timing, power, signal integrity and other challenges at 65 and 45 nm},
  author = {Paul Leventis},
  year = {2008},
  doi = {10.1109/FPT.2008.4762357},
  url = {http://dx.doi.org/10.1109/FPT.2008.4762357},
  researchr = {https://researchr.org/publication/Leventis08},
  cites = {0},
  citedby = {0},
  booktitle = {2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008},
  editor = {Tarek A. El-Ghazawi and Yao-Wen Chang and Juinn-Dar Huang and Proshanta Saha},
  publisher = {IEEE},
  isbn = {978-1-4244-2796-3},
}