A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS

Hao Li, Ganesh Balamurugan, James E. Jaussi, Bryan Casper. A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS. In 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, September 3-6, 2018. pages 238-241, IEEE, 2018. [doi]

Abstract

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